The present invention relates to a method of manufacturing MOS-type transistor devices and semiconductor integrated circuits with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention is also useful in the manufacture of CMOS semiconductor devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 xcexcm, e.g., about 0.15 xcexcm.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires design features of 0.18 xcexcm and below, such as 0.15 xcexcm and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so-called xe2x80x9cshort-channelxe2x80x9d effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and the drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, lightly-doped source/drain extension-type transistor structures have been developed, as described below.
For p-channel MOS transistors of short-channel type, the major limitation on performance arises from xe2x80x9cpunch-throughxe2x80x9d effects which occur with relatively deep junctions. In such instances, there is a wider subsurface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned xe2x80x9cpunch-throughxe2x80x9d current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped drain region is laterally displaced away from the gate by use of a sidewall spacer on the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
Several processing sequences or schemes have been developed for the manufacture of source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the number of processing steps. Conventional processing schemes for making such MOS transistors generally employ disposable spacers made of various materials, e.g., polysilicon, silicon oxides, silicon nitrides, silicon oxynitrides, and combinations thereof.
According to one conventional process scheme, a precursor structure comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode formed on a portion of a surface thereof is subjected to ion implantation prior to sidewall spacer formation for forming lightly- or moderately-doped implants therein. Following post-implantation annealing, sidewall spacers are formed on the pair of opposing side surfaces of the layer stack by first depositing a dielectric spacer material layer over the substrate surfaces and then removing same from the horizontal regions, i.e., the top surface of the gate electrode layer, and the source and drain regions, by anisotropically etching. Such processing results in sidewall spacers left on the gate layer stack side surfaces that have an approximately quarter-circular cross-section. The dielectric sidewall spacers typically remain through the balance of junction formation processing. After sidewall spacer formation, a heavy source/drain implantation is performed, with the gate layer stack and associated sidewall spacers acting as implantation masking materials. As a consequence of the separate implantations, the heavily-doped source/drain regions are laterally displaced from the gate edges by the thickness of the sidewall spacer material and the lightly- or moderately-doped regions beneath the sidewall spacers act as source/drain extensions.
According to another conventional process scheme, which scheme employs disposable (i.e., removable) sidewall spacers, a precursor structure as described above and comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode layer formed on a portion of a surface thereof is subjected to dielectric layer deposition and patterning to form sidewall spacer layers on opposing side surfaces of the layer stack. Opposite conductivity type p- or n-type dopant impurities are then implanted into the substrate using the layer stack with sidewall spacers formed thereon as an implantation mask, to thereby form moderately- to heavily-doped implants. High temperature annealing is then performed to thermally activate the implanted dopant by diffusion and reduce lattice damage due to implantation, thereby forming source/drain regions and junctions at a predetermined dopant density and depth below the substrate surface. The effective length of the channel of such transistors is determined by the width of the gate insulator/gate electrode layer stack and the width of the sidewall spacers formed thereon. After activation annealing, the sidewall spacers are removed, as by etching, and a second implantation process for implanting n- or p-type opposite conductivity type dopant impurities is performed using only the gate insulator layer/gate electrode layer stack as an implantation mask, thereby forming shallow-depth, lightly- or moderately-doped implants in the substrate in the spaces between the deeper, more heavily-doped source/drain regions. Following this implantation, a second activation process, e.g., rapid thermal annealing (RTA), is performed for effecting dopant diffusion and relaxation of implantation-induced lattice damage of the implants, to form shallow-depth, lightly- or moderately-doped source/drain extensions extending from respective proximal edges of the heavily-doped source/drain regions to just below the respective proximal edges of the gate insulator layer/gate electrode layer stack.
In a variant of the above-described process, the sidewall spacers are comprised of a layer of a first, or inner dielectric sidewall spacer material and a layer of a second, or outer, dielectric spacer material. According to the process methodology of this variant, only the second, or outer, dielectric sidewall spacer layer is removed subsequent to annealing for forming the moderately- to heavily-doped source/drain regions. The first, or inner, dielectric sidewall spacer layer is retained for protecting the gate insulator/gate electrode layer stack during subsequent processing, e.g., for contact formation.
Both variants employ removable sidewall spacers as part of an implantation mask for defining the channel lengths, and each incurs a drawback in that the materials conventionally used for the sidewall spacers, such as those enumerated above, frequently are difficult and time consuming to remove by standard etching methodologies, particularly when densified as a result of high temperature processing for post-implantation annealing. For example, and as described in U.S. Pat. No. 5,766,991, removal of silicon nitride-based spacer layers can require etching in a hot phosphoric acid (H3PO4) bath at about 180xc2x0 C. for approximately 1.5 hours. Such long etching time results in reduced manufacturing throughput and the extended exposure to and concomitant attack by the corrosive reagent at high temperature results in undesired etching and defect formation. Moreover, portions of the workpiece substrate not intended to be etched must be provided with an etch-resistant protective barrier layer, e.g., of silicon oxide, prior to etching. However, the etching resistance of the silicon oxide layer to the hot phosphoric acid may be insufficient, in which case the resistance thereof must be increased prior to etching, e.g., by first annealing it at about 900xc2x0 C. in an oxygen ambient. Alternatively, resistance to attack by the hot H3PO4 may be obtained by use of an oxide-polysilicon bilayer. In either case, such requirement for provision of at least one layer for protecting from acid attack disadvantageously adds to processing time, complexity, and fabrication cost. Etching of annealed, densified silicon oxide and/or silicon oxynitride-based sidewall spacer layers is similarly difficult.
Thus a need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors which does not suffer from the above-described drawbacks associated with the difficulty in conveniently and rapidly removing densified sidewall spacers according to conventional etching techniques. Moreover, there exists a need for an improved process for fabricating MOS transistor-based devices which is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above described problems and drawbacks attendant upon conventional processing for forming submicron-dimensioned, MOS and CMOS transistors for use in high-density semiconductor integrated circuit devices, particularly in providing a process utilizing first and second dielectric sidewall spacer layers, the second, or outer, spacers being formed of a dielectric material which is easily and rapidly etched m its as-deposited, undensified state but difficult-to-etch in its annealed, densified state, wherein the undensified second spacers are removed prior to any post-implantation thermal annealing treatment for dopant activation and lattice damage relaxation. The first, or inner, spacers are formed of a dielectric material which is less readily etched than the second, outer spacer layer, whether in its as-deposited, undensified state or its annealed, densified state, and is retained throughout processing for protecting the gate insulator/gate electrode layer stack from attack by corrosive etchant and during subsequent metallization for contact formation.
An advantage of the present invention is an improved method for manufacturing MOS and/or CMOS transistor devices utilizing a removable sidewall spacer.
Another advantage of the present invention is an improved method for manufacturing MOS and/or CMOS transistor devices utilizing a removable sidewall spacer formed of a readily etchable dielectric material.
Another advantage of the present invention is an improved method of manufacturing submicron-dimensioned MOS transistors for use in high-density semiconductor integrated circuit devices at lower cost, higher manufacturing throughput, and increased product yield and reliability than are obtainable with conventional process methodology.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises the sequential steps of:
(a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of the substrate, the layer stack comprising:
i. a thin gate insulating layer in contact with the substrate surface; and
ii. a gate electrode layer formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface;
(b) forming a first pair of insulative, tapered sidewall spacers on each of the pair of opposing side surfaces, the first pair of sidewall spacers comprising a first dielectric material which is relatively etch-resistant in its as-deposited, undensified state;
(c) thermally treating the first pair of sidewall spacers to convert the first dielectric material from its as-deposited, undensified state to its annealed, densified state, thereby increasing the etch resistance of the first pair of sidewall spacers;
(d) forming a second pair of insulative, tapered sidewall spacers on each of the first pair of sidewall spacers, the second insulative spacers comprising a second dielectric material which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally treated, densified state;
(e) selectively introducing dopant impurities of a second, opposite conductivity type into exposed portions of the substrate surface adjacent the first and second pairs of sidewall spacers to form a pair of spaced-apart, heavily-doped implants in the substrate;
(f) selectively removing the as-deposited, undensified second pair of sidewall spacers by etching;
(g) thermally treating the pair of spaced-apart, heavily-doped implants to form a pair of heavily-doped source/drain junction regions in the substrate at a predetermined depth below the substrate surface, each of the heavily-doped source/drain junction regions being laterally spaced from a respective proximal edge of the gate insulating layer by a distance substantially equal to the combined width of the lower ends of the first and second pairs of sidewall spacers;
(h) introducing second, opposite conductivity type dopant impurities into exposed portions of the substrate surface intermediate the gate insulating layer and the heavily-doped source/drain regions to form lightly- or moderately-doped source/drain extension implants; and
(i) thermally treating the lightly- or moderately-doped source/drain extension implants to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in the substrate, each of the shallow-depth, lightly- or moderately-doped source/drain extensions extending from a proximal edge of a respective source/drain junction region to beneath a respective proximal edge of the gate insulating layer.
In embodiments according to the present invention, the method further comprises the step of:
(j) forming a second pair of insulative sidewall spacers over each of the first pair of insulative sidewall spacers, the second pair of insulative sidewall spacers comprising the second dielectric material or a different material.
According to further embodiments of the present invention, step (a) comprises providing a semiconductor substrate of n or p first conductivity type, preferably a silicon wafer substrate, the thin gate insulating layer comprises a silicon oxide layer preferably about 25-50 xc3x85 thick, and the gate electrode layer preferably comprises heavily-doped polysilicon; step (b) comprises forming the first pair of insulative sidewall spacers from a first dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides, the first pair of sidewall spacers being formed with a predetermined tapered profile wherein the widths thereof vary from relatively wide at the lower ends in contact with the substrate surface to relatively narrow at the upper ends thereof; step (c) comprises rapid thermal annealing (RTA); step (d) comprises forming the second pair of insulative sidewall spacers from a UV-nitride deposited in a undensified state, the spacers being formed in a predetermined width profile wherein the widths thereof vary from relatively wide at the lower ends in contact with the substrate surface to relatively narrow at the upper ends thereof, step (e) comprises selectively introducing p or n second, opposite conductivity type dopant impurities by ion implantation, preferably by implanting dopant impurities in an amount sufficient to provide heavily-doped, relatively deep source/drain junctions; step (f) comprises selectively removing the as-deposited, undensified UV-nitride sidewall spacers by etching with dilute aqueous HF, preferably 1:100 HF/H2O at a moderate temperature, at a relatively rapid rate; step (g) comprises rapid thermal annealing at a temperature of from about 1,000xc2x0 C. to about 1,100xc2x0 C. for from about 10 sec. to about 45 sec. to diffuse and activate the dopant impurities introduced during step (e); step (h) comprises introducing p or n second, opposite conductivity type dopant impurities by ion implantation, preferably by implanting dopant impurities in an amount sufficient to provide lightly- or moderately-doped source/drain. extension regions with a shallow junction depth below the substrate surface; and step (i) comprises rapid thermal annealing at from about 900 to about 1,000xc2x0 C. for from about 10 sec. to about 45 sec. to diffuse and activate the dopant impurities introduced during step (h).
According to another aspect of the present invention, a method of manufacturing a silicon-based MOS transistor is provided, which method comprises the sequential steps of:
(a) providing a MOS transistor precursor structure comprising a silicon semiconductor wafer substrate of a first conductivity type and a layer stack formed on a portion of a surface of the wafer, the layer stack comprising:
i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 xc3x85 thick in contact with the wafer surface; and
ii. a gate electrode layer comprising heavily-doped polysilicon formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface;
(b) forming a first pair of insulative, tapered sidewall spacers on each of the pair of opposing side surfaces, the first pair of sidewall spacers comprising a first dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides, said first dielectric material being relatively etch-resistant in its as-deposited, undensified state;
(c) thermally treating the first pair of sidewall spacers to convert the first dielectric material from its as-deposited, undensified state to its annealed, densified state, thereby increasing the etch resistance of the first pair of sidewall spacers;
(d) forming a second pair of insulative, tapered sidewall spacers on each of the first pair of sidewall spacers, the second insulative spacers comprising a UV-nitride material which is readily etched in its as-deposited, undensified state but difficult-to-etch in its annealed, densified state;
(e) selectively implanting dopant impurities of a second, opposite conductivity type into exposed portions of the wafer surface adjacent the first and second pairs of sidewall spacers to form a pair of spaced-apart, heavily-doped implants in the wafer;
(f) selectively removing the as-deposited, undensified U -nitride sidewall spacers by etching with dilute aqueous HF, preferably with 1:100 HF/H2O at a moderate temperature;
(g) performing rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (e), thereby forming a pair of heavily-doped, relatively deep, source/drain junction regions in the wafer, each of the heavily-doped source/drain junction regions being laterally spaced from a respective proximal edge of the gate insulating layer by a distance substantially equal to the combined width of the lower ends of the first and second pairs of sidewall spacers;
(h) selectively implanting second, opposite conductivity type dopant impurities into exposed portions of the wafer surface intermediate the gate insulating layer and the heavily-doped source/drain junction regions to form lightly- or moderately-doped source/drain extension implants therein; and
(i) performing thermal annealing to diffuse and activate the dopant impurities implanted during step (h), thereby forming a pair of shallow-depth, lightly- or moderately-doped source/drain extension regions in the wafer, each of the shallow-depth, lightly- or moderately-doped source/drain extensions extending from a proximal edge of a respective source/drain junction region to beneath a respective proximal edge of the gate insulating layer.
In embodiments according to the present invention, the method further comprises the step of:
(i) forming a second pair of insulative sidewall spacers of predetermined width over each of the first pair of insulative sidewall spacers, the second pair of spacers comprising the UV-nitride dielectric material or a different dielectric material.
According to yet another aspect of the present invention, silicon-based MOS transistor devices formed by the method of the above-enumerated steps (a)-(h) are provided.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.